1. Technical Field
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors and other silicon-based devices. More specifically, the present invention relates to processes for selectively etching silicon for use in such and similar devices.
2. Background
Silicon wet etch is an important process in integrated circuit manufacturing. A specific application for selective silicon wet etch is for introduction of strain for gate formation in the Front End of Line (FEOL) process of transistor construction. Gate oxide, silicon oxide, silicon nitride, polysilicon, and other films may be deposited on silicon to form the transistor gate structures through successive deposition, patterning and etching steps. During this process, through selective masking, the silicon surface is doped with boron, phosphorus, arsenic or other negative or positive silicon biasing elements. The silicon surface is then heated to drive the dopants into the silicon. The monocrystalline silicon is then etched to create channels between the gates for subsequent deposition of a strain inducing silicon alloy such as silicon-germanium (SiGe). It has been found that some amount of strain is beneficial in improving mobility of carriers in, e.g., a MOS transistor channel region. While a number of processes have been disclosed for such strain introduction, improvements are needed to more effectively and controllably etch the trenches into which the silicon alloy will be deposited and to more effectively and controllably create in and apply to the channels a desired amount of strain. The amount of strain desired can be difficult to obtain if the strain inducing silicon alloy contains too many dislocations in the crystalline structure, since the dislocations relieve strain and/or do not generate sufficient strain when deposited.